The conventional imaging system includes an analog-to digital (A/D) converter for converting analog signals output from an imaging element to digital signals (A/D conversion), a data processing section for processing the image data, a memory for storing the image data, and a memory control section, wherein the image data output from the A/D converter or the data processing section is stored in the memory or the image data is transferred from the memory to another data processing section by means of the memory control section (refer to e.g., Japanese Laid-Open Patent Publication No. 10-178612).
FIG. 28 is a block diagram of a configuration of such a conventional imaging system. As shown in FIG. 28, the imaging system 200 includes an optical lens 211, a solid-state imaging element 212, a drive circuit 213 of the solid-state imaging element 212, an analog circuit 214, an A/D conversion circuit 215, a memory controller 216, a Synchronous Dynamic Random Access Memory (hereinafter referred to as “SDRAM”) 217 serving as a memory circuit, a camera signal processing circuit 218, a JPEG compression circuit 219, a display circuit 220, a liquid crystal display unit 221, a card controller 222, and a recording medium 223.
The operation of the imaging system 200 will now be described. When light enters through the optical lens 211, the solid-state imaging element 212 is irradiated with the light. The solid-state imaging element 212 photoelectrically transfers the light irradiating thereon, and outputs the obtained electric signals (analog signals) to the analog circuit 214. The analog circuit 214 performs the analog signal process on the analog signals output from the solid-state imaging element 212, and outputs the processed analog signals to the A/D conversion circuit 215. The A/D conversion circuit 215 converts the analog signals output from the analog circuit 214 to a digital signal. Here, the digital signals output by the A/D conversion circuit 215 is signals before the digital signal process is performed thereon, and thus is referred to as raw data (RAW). The A/D conversion circuit 215 outputs the raw data to the memory controller 216. The memory controller 216 then stores the raw data, which is output from the A/D conversion circuit 215, to the SDRAM 217.
The memory controller 216 then reads the raw data stored in the SDRAM 217 and transfers the raw data to the camera signal processing circuit 218. The camera signal processing circuit 218 performs camera signal process on the raw data read out from the SDRAM 217, and generates YC data (YC) for recording and for displaying expressed by a luminance signals (Y) and a chrominance signals (C) The camera signal processing circuit 218 performs a zoom process and the like on the raw data to generate the YC data for displaying. The memory controller 216 reads the YC data from the camera signal processing circuit 218 and stores such YC data in the SDRAM 217.
Next, when compressing and storing the YC data in the SDRAM 217, the memory controller 216 reads and outputs the YC data for recording stored in the SDRAM 217 to the JPEG compression circuit 219. The JPEG compression circuit 219 performs the compression process according to the Joint Photographic Experts Group (JPEG) standard, and generates coded data (JPC). The memory controller 216 reads the coded data from the JPEG compression circuit 219, and stores the coded data in the SDRAM 217.
When displaying the captured image on the liquid crystal display unit 221, the memory controller 216 reads the YC data for displaying stored in the SDRAM 217 and transfers such YC data to the display circuit 220. The display circuit 220 converts the YC data to signals (display data) for displaying and outputs the signals to the liquid crystal display unit 221. The liquid crystal display unit 221 displays the image represented by the signals for displaying.
The card controller 222 is connected to the SDRAM 217 and reads out the JPEG coded data stored in the SDRAM 217 and writes such data into the recording medium 223.
As mentioned above, in the conventional imaging system, many data such as raw data, YC data, coded data, display data and the like are transferred between the memory and the memory controller. Thus, the power consumption at the interface of the memory and the memory controller becomes large, that is, the power consumption becomes large.
Further, in the conventional imaging system, the processing speed tends to be slow due to large amounts of data to be handled. In order to increase the processing speed, either the operation frequency must be increased or the processing performance of the circuit must be enhanced, but in either case, the power consumption increases. In other words, it is difficult to increase the processing speed without increasing the power consumption.
It is therefore an object of the present invention to provide an imaging system in which the power consumption is small and the speed of processing the data is fast.